The present disclosure relates generally to semiconductor devices and methods for fabricating the same, and more particularly relates to a semiconductor device including a MISFET (metal insulator semiconductor field effect transistor) having offset spacers, and a method for fabricating the same.
In recent years, with the increasing degree of integration, increasing functionality, and increasing speed of semiconductor integrated circuit devices, progress has been made in the refinement of MISFETs (hereinafter referred to as MIS transistors). Accordingly, the trend has been to form a gate electrode having a shorter gate length (e.g., in the order of 30 nm) and a thinner gate insulating film (e.g., having a thickness of the order of 2 nm).
A technique has been proposed in which, in order to enhance the driving capability of a MIS transistor, a stressor film is formed after the removal of outer sidewalls so as to be brought closer to a channel region by the width of each of the removed outer sidewalls, and a stress arising from the stressor film is efficiently applied to the channel region along the gate length (see, for example, Japanese Unexamined Patent Application Publication No. 2007-49166). A conventional fabrication method for a semiconductor device will be described hereinafter with reference to FIGS. 6A through 6C. FIGS. 6A through 6C are cross sectional views taken along the gate length and showing essential acts in the conventional fabrication method for a semiconductor device in a sequential order.
First, as shown in FIG. 6A, an isolation region (not shown) is selectively formed in an upper part of a semiconductor substrate 100. Thus, a semiconductor region 100x is formed in the upper part of the semiconductor substrate 100 so as to be surrounded by the isolation region. Thereafter, a well region 101 is formed in the upper part of the semiconductor substrate 100. Then, a gate insulating film 102 and a gate electrode 103 are sequentially formed on the semiconductor region 100x. 
Subsequently, offset spacers 104 are formed on the side surfaces of the gate electrode 103, and then extension implantation regions 105a are formed in parts of the semiconductor region 100x located laterally outward from the offset spacers 104. Thereafter, sidewalls 107A composed of inner sidewalls 106 and outer sidewalls 107 are formed on the side surfaces of the gate electrode 103 with the offset spacers 104 interposed between the sidewalls 107A and the gate electrode 103, and then source/drain implantation regions 108a are formed in parts of the semiconductor region 100x located laterally outward from the sidewalls 107A.
Next, as shown in FIG. 6B, conductive impurities contained in the extension implantation regions 105a and the source/drain implantation regions 108a are activated by heat treatment, thereby forming extension regions 105 and source/drain regions 108. Thereafter, the outer sidewalls 107 are removed by wet etching using thermal phosphoric acid.
Next, as shown in FIG. 6C, a first metal silicide film 109 is formed on the gate electrode 103, and second metal silicide films 110 are formed on the source/drain regions 108. Thereafter, a stressor film 111 is formed on the entire surface area of the semiconductor substrate 100.
Subsequently, an interlayer insulating film 112 is formed to cover the stressor film 111, and then a contact hole 113 is formed in the stressor film 111 and the interlayer insulating film 112 to reach the second metal silicide film 110. Thereafter, a barrier metal film 114 is formed on the bottom and side wall of the contact hole 113, and then a conductive film 115 fills the contact hole 113 with the barrier metal film 114 interposed therebetween. In this way, a contact plug 115A is obtained wherein the conductive film 115 fills the contact hole 113 with the barrier metal film 114 interposed therebetween. Thereafter, a wire 116 is formed on the interlayer insulating film 112 so as to be connected with the contact plug 115A.